The i4003 Shift Register

Intel 4003 shift register

The last of the original MCS-4 chips I need to emulate for the Busicom 141-PF re-creation is the i4003 shift register. I expected this to be simple: it's a 10-bit shift register with a clock input, a serial input, a serial output, 10 parallel outputs, and a parallel output enable input. How complex could this be?

In my mind I was picturing one Verilog always block for the shift register and a continuous assignment statement for the output enables. Four lines of code plus the module definition.

As it turns, the i4003 shift register is a more complicated chip than I expected.

What I suspect Intel wanted to implement was an array of edge-clocked D flip-flops similar to the 74164 depicted here, with added tri-state output buffers.

Logic diagram for the 74164 shift register

However, it appears they also wanted to be able to drive the serial data input and the CP (clock pulse) lines from the same output port without risk of setup time violations. Thus the CP input signal is internally delayed by passing it through a series of inverters. This allows the serial data input to arrive as much as 250ns after the assertion of the CP (clock pulse) input and still meet the required timing. This, then, requires the serial data output to be updated only after the deassertion of CP so that multiple i4003s can be cascaded using a common clock pulse signal.

Since there is no way to guarantee such delays in an FPGA,  my emulation of the i4003 uses a high-speed system clock input to drive a delay timer. The CP input is sampled on each rising edge of the system clock and compared with the CP value saved 250ns previously. If they are different a counter is started; when the counter indicates 250ns has passed the saved value is updated. The rising edge of the delayed CP causes the entire register to shift one bit, adding the serial input to the low end of the shift register. On the falling edge of the delayed CP another FF is updated from the high end of the shift register, and that is used as the serial output. This emulates the behavior of a real i4003 chip reasonably closely.