Semi-final CCLK layout

Here's a screenshot of the current, and potentially final, layout of the FPGA configuration clock line (CCLK in the Xilinx docs, labeled CFG_SCK on my schematic and board).

The TQFP-144 footprint in the upper left corner is U1, the Spartan 6 FPGA. The WSON-8 footprint in the lower center (with the big "9" on its heatsink pad) is U2, the S25FL128L Flash ROM. For scale, U1's pads are on 0.5mm centers, while U2's pads are on 1.27mm centers.

The CFG_SCK track is 0.3mm wide, giving it a characteristic impedance of 50 ohms.

The two large resistors near the lower left corner of U2 form the Thevenin terminator, should it be needed. They are 0603 packages due to their dissipation of 109mW when the CCLK output is driven to either rail (Vcco_2 is 3.3V). The other components around U2 are 0402 packages, including the pads for the 0 ohm jumper.

Xilinx UG380 Figure 2-22

The reason I've chosen this layout is that without the jumper in place there is a minimum of disruption of the track between the FPGA and the Flash ROM. With any luck this is how it'll stay. With the jumper in place it bears a passing resemblance to the specified layout with a short 2mm stub to the ROM in the middle and the terminator at the end.

What difference does a probe make?

When I bought my 1 GHz LeCroy digital oscilloscope in June of 2012 (omg, was it really almost 7 years ago??) it came with a set of four LeCroy PP007-WR probes. These have served me well but they have limitations. The first is that they're only rated to 500 MHz, the second is that their input capacitance is 9.5 pF.

Why on earth would that matter? After all, I'm not working with 1 GHz signals, so why would a 500 MHz limitation be a problem? And 9.5 pF is practically nothing.

Experimenting with Micro-Cap

While looking for more info on IBIS I came across a mention that the free demo version of Micro-Cap from Spectrum-Soft.com would convert an IBIS file to Spice. This is true! Not only did it import the IBIS definition for the Spartan-6 CCLK output, it will also run my simulation. The free demo is cripple-ware so it runs quite slowly and has many other limitations, but it does run and is sufficient to run my tiny circuit.

Assuming the simulation is reasonably accurate, it tells me is that my previous attempts at simulation were valid: with a 50 ohm microstrip transmission line of about an inch (167ps) in length, it will act as a lumped circuit and no termination is required. In fact, with Thevenin termination the signal at the FPGA pin looks worse than the unterminated circuit due to the reduced output swing and thus narrower noise margins.

I'm still going to lay out pads for the Thevenin terminating resistors just in case, but I won't plan to install them before testing. And I definitely won't include the source termination resistor.

Unfortunately the Spice library Micro-Cap generates isn't acceptable to LTspice: there are some weirdnesses in how it names nodes. I suspect I could hand-edit them to be more standard. But what I'm really more interested in is using the tables it generates to validate my IBIS-to-Spice extractor, which I'm hoping to still finish and publish.

Converting IBIS to Spice

One of the things that has been frustrating me is my inability to properly simulate the CCLK I/O on the Spartan-6 FPGA. Many chip vendors don't want to reveal too much about the structure of their devices, so rather than giving Spice definitions for their interfaces they provide IBIS (I/O Buffer Information Specification) definitions. With the proper tools, IBIS allows for efficient simulations without having to simulate the device's entire I/O buffer circuit.

The problem is that none of the freely available Spice circuit simulators understands IBIS. Commercial simulators are available, but the cheapest one I found cost almost $300 for a 3-month license and some run into the tens of thousands of dollars.

CCLK Terminator Three

After much debate and vacillation, I've decided how I'm going to handle the CCLK circuit termination.

For detailed background, read my posts The CCLK Terminator and Terminator Two.

Back to the P170-DH replacement PCB

It's been months since I worked on the replacement PCB for the P170-DH calculator. Both personal and work life has conspired to keep me away, but also I've been frustrated trying to finish the routing. Sometimes I'd open the PCB layout and stare at it for a while, then close it again having made no changes.

Recently I've been reading through this blog, and the desire rose to finish up projects I've left dangling for too long. I tried to beat down that feeling, but I think I may have failed.