KiCon 2019: The KiCad Conference

A couple months ago I came across an announcement for a conference for KiCad users and developers in Chicago called KiCon. Since I now use KiCad for my schematic entry and PCB layout, I thought this would be fun to attend. So here I am in Chicago!

Simulating the VFD Grid/Anode driver

I was reading through an old posting about the VFD Grid and Anode driver circuit I'm planning to use, when it occurred to me that the resistor between the base of the PNP transistor and the collector of the NPN transistor might not be necessary. This is labeled R1 in the schematic to the right.

To calculate the desired resistance I'd done a bunch of hand calculations in my notebook, trying various combinations of target currents and resistor values. I started to do yet another with R1 set to zero when it occurred to me that this would be easier to do in simulation. At first I entered this circuit into LTspice using 2N3904 and 2N3906 transistors, as these are standard parts in the LTspice library. The simulation results matched my hand-calculated numbers, which gave me confidence that I'd done the calculations properly. I'm driving both transistors into saturation, and my turn-off times are anything but critical, so the choice of transistor isn't critical.

Then I wondered how closely this approximation matched the real Toshiba RN4604. At first I thought this would be a challenge, as the process for creating a Spice model description for a transistor from its datasheet isn't that easy. Wouldn't it be nice if Toshiba provided a Spice model? Well, they do, and it's available for download from their website. To make it easier to probe the base current of Q1A (Q1 in the Spice schematic) I extracted the transistor models from the subcircuits that add the built-in bias resistors and substituted them into my circuit.

My original plan had been to turn on Q1A by passing about 500 µA through its base. This was based on the spec'd saturation I_CE of 5 mA with I_BE of 250 µA, giving an h_FE of 20. In the actual application I've found a grid draws about 6 mA and its 10K pull-down resistor will draw another 3 mA, so I doubled I_BE for an I_CE of 10 mA. If I eliminate R1 the base current jumps to 606 µA. But this puts almost the full 30 volts across the input (between pins 1 and 2); the datasheet graphs stop with an input voltage of 9 V. Even with the original R1 of 10K the input voltage is almost 25 V. So I'm thinking I should revisit this.

Looking at the h_FE graphs I see the worst-case (at -25°C!) current gain at 30 mA is about 100. Of course this is in the transistor's linear region, but it implies that with a base current of 300 µA and a collector current of only 10 mA the thing will be saturated. So I tweaked my Spice simulation to sweep the value of R1 from 100 ohms to 150 Kohms. I graphed the base and collector currents of the transistor, along with the "input" voltage (the difference between pins 1 and 2 on the package). I also changed the collector load resistor to 1 KΩ to get about 30 mA collector current if the transistor was saturated. This would make it more obvious when decreasing the base drive would start having a significant effect on the collector current.

The trick to interpreting these graphs is to remember that this is a PNP transistor in a common-emitter configuration, so the base and collector currents are negative. Thus a rise in the graph means less current. Also, the horizontal scale represents ohms, even though it's reported in volts. So the "100KV" tick actually represents 100 KΩ.

It's pretty obvious I don't need 500 µA of base current. In fact, it looks like I could make R1 as high as 100 KΩ and still drive this transistor into saturation. Setting R1 to 63 KΩ gives me 250 µA of base current, while 47 KΩ gives me 295 µA. I'll probably choose 47 KΩ to allow a generous margin for variations in bias resistor values, which can vary as much as ±30% in absolute value in the RN4604.

Semi-final CCLK layout

Here's a screenshot of the current, and potentially final, layout of the FPGA configuration clock line (CCLK in the Xilinx docs, labeled CFG_SCK on my schematic and board).

The TQFP-144 footprint in the upper left corner is U1, the Spartan 6 FPGA. The WSON-8 footprint in the lower center (with the big "9" on its heatsink pad) is U2, the S25FL128L Flash ROM. For scale, U1's pads are on 0.5mm centers, while U2's pads are on 1.27mm centers.

The CFG_SCK track is 0.3mm wide, giving it a characteristic impedance of 50 ohms.

The two large resistors near the lower left corner of U2 form the Thevenin terminator, should it be needed. They are 0603 packages due to their dissipation of 109mW when the CCLK output is driven to either rail (Vcco_2 is 3.3V). The other components around U2 are 0402 packages, including the pads for the 0 ohm jumper.

Xilinx UG380 Figure 2-22

The reason I've chosen this layout is that without the jumper in place there is a minimum of disruption of the track between the FPGA and the Flash ROM. With any luck this is how it'll stay. With the jumper in place it bears a passing resemblance to the specified layout with a short 2mm stub to the ROM in the middle and the terminator at the end.

What difference does a probe make?

When I bought my 1 GHz LeCroy digital oscilloscope in June of 2012 (omg, was it really almost 7 years ago??) it came with a set of four LeCroy PP007-WR probes. These have served me well but they have limitations. The first is that they're only rated to 500 MHz, the second is that their input capacitance is 9.5 pF.

Why on earth would that matter? After all, I'm not working with 1 GHz signals, so why would a 500 MHz limitation be a problem? And 9.5 pF is practically nothing.

Experimenting with Micro-Cap

While looking for more info on IBIS I came across a mention that the free demo version of Micro-Cap from Spectrum-Soft.com would convert an IBIS file to Spice. This is true! Not only did it import the IBIS definition for the Spartan-6 CCLK output, it will also run my simulation. The free demo is cripple-ware so it runs quite slowly and has many other limitations, but it does run and is sufficient to run my tiny circuit.

Assuming the simulation is reasonably accurate, it tells me is that my previous attempts at simulation were valid: with a 50 ohm microstrip transmission line of about an inch (167ps) in length, it will act as a lumped circuit and no termination is required. In fact, with Thevenin termination the signal at the FPGA pin looks worse than the unterminated circuit due to the reduced output swing and thus narrower noise margins.

I'm still going to lay out pads for the Thevenin terminating resistors just in case, but I won't plan to install them before testing. And I definitely won't include the source termination resistor.

Unfortunately the Spice library Micro-Cap generates isn't acceptable to LTspice: there are some weirdnesses in how it names nodes. I suspect I could hand-edit them to be more standard. But what I'm really more interested in is using the tables it generates to validate my IBIS-to-Spice extractor, which I'm hoping to still finish and publish.

Converting IBIS to Spice

One of the things that has been frustrating me is my inability to properly simulate the CCLK I/O on the Spartan-6 FPGA. Many chip vendors don't want to reveal too much about the structure of their devices, so rather than giving Spice definitions for their interfaces they provide IBIS (I/O Buffer Information Specification) definitions. With the proper tools, IBIS allows for efficient simulations without having to simulate the device's entire I/O buffer circuit.

The problem is that none of the freely available Spice circuit simulators understands IBIS. Commercial simulators are available, but the cheapest one I found cost almost $300 for a 3-month license and some run into the tens of thousands of dollars.

CCLK Terminator Three

After much debate and vacillation, I've decided how I'm going to handle the CCLK circuit termination.

For detailed background, read my posts The CCLK Terminator and Terminator Two.