A second i4004 design flaw?

The designers of the Intel 4004 CPU were innovative and talented, but like all humans they make mistakes. One, affecting the Instruction Pointer counter, I described in a previous post. The more I look at this, the more I think this is a second mistake.


The incrementer has to perform three 4-bit additions with carries for each instruction fetch. Since it's always adding 0x001, the logic is simpler than the adder in ALU.

Here's one of the four XOR gates in the incrementer. The red net entering the lower left is Data-In; the red net entering the lower right is Carry-In. The blue net going out of frame on the upper left is Data-Out. The red net entering the upper right is N0325, the attenuated CLK1 signal, which is used to pre-set the Carry-In signal.

If Carry-In is high, this circuit inverts the input data. Conversely, if Carry-In is low, this circuit doesn't invert the input data. Why this arragement? The output of the incrementer drives the read-sense lines of the DRAM array, which get inverted before being written to the array. Thus the incrementer needs to invert the input data to cause the array to receive the intended values. Clear? Yeah, the repeated inversions are confusing to me too.

Since the Carry-In signal is pre-set every CLK1 pulse, the carry generation logic need only pull this circuit low if a carry into this bit is needed. Four sets of pass FETs form NAND gates that calculate the carry inputs in parallel. The carry out of the high-order bit is derived by the NAND gate formed by T1018, T0030, T0031, T0032, and T0026. This high-order carry out is fed back into the low-order carry input in the next cycle through a pair of inverting latches; the first latching on CLK2, the second on CLK1.

The flaw is in the circuit that calculates the high-order carry out. When CLK1 goes high, it turns on T0972 which turns off T0995, T1059, and T0026, preventing shoot-through via all the carry pre-set FETs. All, except via T1060. I suspect T1060 exists because T0026 is misplaced; it should be connected between T1018 and Vss. Positioned where it is, turning it on caused the charge on gate of T1048 to be drawn down. Adding T1060 causes both sides of T0026 to be pre-charged, but results in the shoot-through problem.

BTW, this leads me to reconsider the purpose of T0047, the always-on pass FET in series with CLK1. I'm back to thinking that its purpose is to delay the turn-on of the pre-set FETs T1081 through T1085 and T1060 until after T0972 has a chance to turn off T0995 and T1059. This would suggest the designers were aware of the shoot-through problem, and probably fixed (or prevented) 5 of the 6 cases. I'll definitely have to put a 'scope on this.