I finished Lesson 2 of FEDEVEL Academy's Advanced PCB Layout course yesterday. As I expected, there ratio of review to new material (for me) is shifting toward the new stuff. There were a couple of confusing points, like the the instructor's strong recommendation to use a separate via for each power and ground connection on a BGA while watching him demonstrate routing two such adjacent balls to a shared via. Some of the recommendations offered were things that I had read elsewhere, but it was nice to have it explained from another person's viewpoint.
And there were a couple of "Wait, what?" moments. 😯
This week we covered topics like basic board stackups, initial BGA fanouts, and some introductory information on DDR3 DRAM layout.
All of this is of keen interest to me right now, and I've already become somewhat familiar with DDR3 routing. For example, I'd read that you could swap byte lanes to a DRAM as long as you also swapped related nets. This means you can swap DQ0-DQ7 with DQ8-DQ15, as long as you also swap DM0 with DM1 and the DQS0 pair with the DQS1 pair. This can make routing the PCB easier. I'd also read that you could swap data bits within a lane, like swapping DQ3 and DQ4 for the same reason. What I didn't know is that you can not swap the low-order bit with another bit within the same lane. Assuming no lane swapping for clarity, this means DQ0 on the Zynq must connect to DQ0 on the DRAM, and DQ8 on the Zynq must connect to DQ8 on the DRAM.
When I heard this I actually skipped back in the video to the start of the discussion of bit swapping within a byte lane to make sure I heard it correctly, and that I'd heard all of it.
The instructor explained this by referring to the manual for the processor being used in the example, an Intel i.MX6. I wanted to be absolutely sure this wasn't some quirk in the i.MX6 processor, so I looked this up in the manuals for both the Zynq-7000 and the Micron DRAM chip I'm planning to use. These explained in detail how the low-order data bit is used during initialization to determine how to compensate for the skew in the wiring between the controller circuitry and the DRAM's circuitry. If the low-order bit in the byte lane is swapped with a different bit, this skew compensation discovery can't happen. Hello, nonfunctional board!
Wow. Maybe I would have noticed this in the manuals before I routed my board, but I suspect not. If I get nothing else out of this course, this one tidbit was worth the cost. Literally, as I expect the cost of respinning a pair of assembled boards to be about the same as the cost of this course.
When I signed up for this course I weighed the "Online and Download" option versus the purely "Online" option I got. This would have given me access to all the videos at once, rather than having them parceled out one lesson every 7 days. I didn't, primarily because the cost would have been double for something I wasn't sure would benefit me. After two lessons I'm content with what I got. The instructor covers a lot of material in a two hour lesson. I'm finding that I can watch about 30 to 40 minutes before I need to pause. Sometimes he's giving Altium hints and tricks, and I stop and think about how I could do something similar with KiCad. Sometimes he's talking about something I'm already familiar with, and I find myself not paying close enough attention to glean the useful bits. More frequently now, he's presenting material that is new to me, and I need time to absorb it and think about how I can apply it to my projects. He also suggests "assignments" for the students to do, and I'm just about to the point in schematic development where I can begin to try his techniques. So one class a week is working for me.
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