Saturday, June 8, 2013

P-Channel Experiments

A month or so ago I was discussing with Tim McNerney how a P-channel version of the i4004 might be constructed using the BSS84DW dual-FET. Recently I ordered some parts from Digi-Key for another project, and added 10 of these parts and prototyping adapters for them. It's painful when the FETs cost $4 and the adapters $16, but there's no way to experiment with them without the adapters or other PCB.

This afternoon I found time time to play around with them. I set up cascade of BSS84DWs as inverters, much as I did with the FDV301Ns earlier. The PIC I'm using to generate the input to the cascade can't run at 15V, but the input only needs to rise above the Vgs(th) of the first FET. Since the BSS84DW is a P-channel device, "above" is actually negative. To achieve this I connected one lead of the FET pairs to the +5V output of my bench supply and a pull-up resistor between the other lead and the -10V supply output. This means the FETs see 15V across them, just as with a real i4004. From the FET's point of view, the PIC pulls the Gate lead to Vss when it outputs a "1", and to -5V when it outputs a "0".

Propagation lag through each stage using 4.7K Ohm pull-up resistors is a respectable 48ns. A similar chain using FDV301Ns has a propagation lag of 58ns, but with a Vdd of only 5V there's only 1/3rd of the current available to charge the gate capacitance. Switching to 1.5K Ohm pull-ups gives the FDV301N chain a lag of only 18ns, which makes sense given its significantly lower gate capacitance. This suggests an implementation using BSS84DW FETs would probably draw about three times the current as my current design.

Thus far I've only mounted 5 of my 10 BSS84DWs. I can't imagine doing this without a microscope -- these things are just freaking small: 1.30 x 2.15 mm. With leads on 0.65mm centers I didn't even try to solder them even with my finest iron. Instead I immediately went to solder paste and hot air. This makes things so much easier, as the surface tension of the melted solder causes the whole package to shift so the leads align perfectly with the pads. PCB routing of a board based on these would be a challenge, as there's no room to run traces between the pads: the recommended footprint leaves only 0.23mm (~9 mils) between the edges of adjacent pads.

Eventually I'll get around to mounting the rest of these, and maybe I'll try to breadboard a DRAM cell with them.

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