As promised, I breadboarded the same circuit I fed to the simulator. The curves look really close, but the scale is all wonky.
Here's the schematic (click to embiggen):
Here's a piece of the simulation run results:
The green trace falling from 4.5V to 0V on the left is the simulated clock source, which is input to the first FET, T1. The output of T1 is the blue trace, which briefly falls below ground, then rises to the threshold voltage of T2 before being held there as the "Miller charge" in T2 is dissipated, then begins its climb toward +5V.
An easy way to measure propagation delay through this circuit is to measure the time between the two falling edges of the outputs from T2 (red) and T4 (violet). T2, T3, and T4 are interior FETs in the chain, and thus are somewhat insulated from the characteristics of the driving signal and termination. This simulation shows a time difference of about 400ns, which gives a per-stage propagation delay of about 200ns. This is a bit long in a system like the 4004 where the clock pulse width may be as short as 380ns and the cycle time 1.35us.
Now, an FDV301N is documented to have a turn-off time of about 8ns, so it's all about moving charges around. Lowering the pull-up resistor value from 10K to 4.7K would cut the delays by half. Originally I wanted to hit the 4004's documented power consumption, but with connection lengths measured in inches rather than microns, and using stock components, that's a lost cause. If I was using an open-collector TTL output I'd use a 4.7K Ohm pull-up resistor without second thought, so that's not unthinkable.
But let's look at real timing on the bench, again with 10K pull-ups:
The colors are different: the output of T1 is yellow instead of blue, and the output of T4 is green. Also, I've used an external trigger that shows up only as the triangular mark under the first division mark in from the left edge. But otherwise it looks very similar, doesn't it? As it should, if the simulation is accurate. But take a look at the time scale. The scope's timebase was set to 50ns per division, while the simulation is 100ns per division. The time difference from T2 to T4 is now 200ns, giving a real-world propagation delay of 100ns per stage, not 200ns. Wow.
I guess it could be that the components really are 2x better than the book values the simulation uses. But I wouldn't think that would result in a x2 difference. Especially when you consider that every connection on the solderless breadboard itself adds a bunch of capacitance, and my scope probes add 10pF each, none of which are considered by the model.
This is why I switched from Electrical Engineering to Software Engineering as a career.