What does a 4004 DRAM cell look like? To the right is a clip of the 4004 schematic. Shown are four transistors. From bottom-left to top-right, they are the write-enable transmission gate, the storage element, the read-sense transmission gate, and the column precharge.
To write a single bit of data, we drive the Data In line (the left vertical wire) to the state of the data bit you want to store. Once it's stable (which takes time, nothing is instantaneous) we assert the Write Enable line (bottom horizontal wire) which turns on the write-enable transmission gate. The signal we want to preserve, high or low, passes from the Data In line, through the transmission gate, and charges the storage element's gate-to-channel capacitance. For those who just glazed over, this is the juggler tossing the ball into the air. After waiting 500ns for that to stabilize (that's 500 billionths of a second) we turn off the Write Enable line. The charge is now trapped in the transistor forming the storage element.
To read the bit back, we first precharge the Data Out line (the middle vertical wire) to the high state by briefly turning on the precharge transistor on at the top. We then turn on the Read Enable line (top horizontal wire), which turns on the read-sense transmission gate. If the storage element is holding a high value it's turned on, and will pull the stored charge on the Data Out line to ground through the read-sense transmission gate; if it is holding a low value it's turned off and nothing much will happen to the Data Out line and it will remain high. In the process we've inverted the sense of the signal (a stored high results in a low on the Data Out line, and vice versa) but we can fix that easily by using another transistor as an inverter (not shown); this also provides a stronger signal than the rather weak charge on the Data Out line.
Eventually the charge on the storage element's gate-to-channel capacitor will leak away. In the juggler analogy, the ball will eventually fall to earth if we don't toss it up again. So periodically we have to refresh the bit stored in the storage element transistor. We do this by reading the value and writing it back. The 4004 refreshes each DRAM row at least every 512us, which is pretty fast -- modern DRAM only needs each row refreshed about every 4ms.
But isn't that more than three transistors? Yes, but it's only three transistors per cell, the others are shared across the entire row or column. For example, there's only one precharge transistor and one inverter transistor per column. In the Instruction Pointer array there are four 3-transistor cells per column, and in the Scratchpad array there are eight 3-transistor cells per column. And the circuits that drive the Read and Write Enable lines are shared by all cells on the same row, which is 12 cells in the Instruction Pointer array and 8 cells in the Scratchpad array. In today's chips there are several thousand cells in each row and each column. But in 1970, a 32 x 32 array like the Intel 1103 DRAM chip was considered pretty impressive.