Sunday, June 10, 2012

Breadboarding a 2-bit counter

After having lots of fun breadboarding a single DRAM cell, I wanted to try something more complex. I settled on a counter circuit used in several places. The Instruction Pointer uses two of these in cascade to determine which of the four rows to use (thus forming the 4-deep call stack), and both the Instruction Pointer and the ScratchPad arrays use these, in two- and three-deep cascades respectively, to track which DRAM row to refresh next.

Here's the two-deep Effective Address Counter from the Instruction Pointer:

By asserting the two signals in the lower right corner in the proper pattern, this counter will sequence the two signals in the upper left corner through the four possible states. Note that the circuit is really two stages of a single sub-circuit in cascade.

I wanted to do this circuit for a couple of reasons. One is that it makes use of  transmission gates in two places in each stage. Unlike the DRAM circuit, where special care is taken to store and refresh a charge, this is much more like the rest of the uses in the system. Another reason is that this shows the use of stacked transistors to form a NAND gate. This is one of the places where a 4-terminal FET is not necessary, but it's not yet clear to me if the FDV301N would work; if the gate of the upper transistor in the stack is pulled to ground, the S-G diode in the FDV301N will conduct and pull the source to ground too. It's circuit-dependent whether this is a bad thing or not. Here it might not be a problem -- that's one of the reasons for the experiment!

Here's what the circuit  looks like on a solderless breadboard:

In the lower left corner of the photo you can see the PIC driving the control signals, with its 16MHz oscillator can to its left. On the right side, the lower two rows are the sub-circuit on the right side of the schematic, and the upper two rows are the sub-circuit on the left side of the schematic.

As was the case with the breadboarded DRAM circuit, this works when clocked at about the same rate you'd see in a real Intel 4004. However, for someone used to TTL and CMOS circuits with push-pull outputs, the signals looked really ragged. Both the FETs I'm using turn on at around 1V, so it really doesn't matter that much how fast the signals rise once the FETs they drive turn on, but it makes me worry about what happens when the loading goes up.

Also of concern is the difference between a breadboarded circuit like this and the same circuit on a PCB. When I was a teenager I found it greatly disappointing when an analog design that seemed to work fine when hand-wired failed to work when implemented on a PCB. I just didn't know enough about stray capacitances and coupling effects. This was a big reason I switched to playing with digital electronics rather than analog, and eventually went into software engineering instead.

I've often said that the measure of maturity is not how much you know, but how aware you are of what you don't know. Here, I'm aware that the solderless breadboard adds lots of stray capacitance to the circuit -- as much as 25pF per connection, I've read. This is both good and bad. Good, in that a signal that swings fast enough on the breadboard will probably swing at least that fast on a PCB. Bad, in that I don't know whether the DRAM circuit is depending on having that extra capacitance on the storage element's gate to hold its charge. This is the reason the layout I'm planning for the first board has a footprint for a small capacitor at each point where this might be a factor. If it works without the caps, great; if not, I'll be able to add them in later.

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