What sort of a connector should I use? Let's start with the nature of the interface. To simplify the serial interface logic in the FPGA I'd like to use some sort of synchronous clocking. This avoids having to over-sample the signal to detect the leading edge of the start bit, at the cost of an extra clock signal. If the signals were in the MHz range I'd want to use differential signaling, but at lower speeds (and voltages) single-ended signaling should be sufficient. That brings the width down to five wires:
- Signal ground
- Data from P170 to CPU board stack
- Data from CPU board stack to P170
- Synchronous clock (or two?)
- P170 FPGA boot select
I intend the rebuilt P170 to emulate a Busicom 141PF calculator with all the MCS-4 chips and other logic implemented in an FPGA. But I also want to use it as an I/O peripheral, so I need to select which bitstream gets loaded into the FPGA. My plan is to use one of the pins of the connector as a boot select input, so if the P170 is powered on with nothing connected to the interconnect it boots as a standalone device, but if the boot select pin is grounded then it boots as an I/O peripheral.
Thus I need 5 pins, or 6 pins if I use separate clocks for each data path.
Right now I'm thinking the 6-pin mini-DIN connector used for PS/2 mice and keyboards fits the bill well. It's small, easily available, and I can easily find male-male straight-through cables to connect the two devices. On the CPU board stack I can use a PCB-mount connector, but in the P170 the PCB doesn't reach the edges of the case. For this I can use a chassis-mount connector like the one to the right. That opens more options for placing the connector, as it doesn't need to be aligned with the PCB.
The Digilent S3E reference board and PS/2 PMOD bring the FPGA signals out through series resistors. I'm not sure that's really sufficient ESD protection. I'm looking at the TI TPD2S017 ESD protection chip. This includes a small series resistor with transient voltage suppression diodes. I'm also considering the TXB0104 voltage translator, which would also solve the issue of prematurely powering the FPGA through its I/O pins. Both of these are bidirectional devices, so I'm not committed to any particular direction of transmission.