Tuesday, July 10, 2018

Demonstrating the SAP-1 Program Counter bug

Simulation is all fine and well, but the proof is comparing the results of the simulation with the real circuit. So I did just that.

When my order from Jameco arrived I found five F-74107PC Master/Slave J/K flip-flops. I suspect the "F" logo means they were manufactured by Fairchild, and they have date codes from 1978. I also received five SN74LS107A edge-clocked J/K flip-flops manufactured by Texas Instruments. Over the US 4th of July holiday I wired up the circuit, only to discover I'd neglected to order a 7404 hex inverter.

The SAP-1 design generates the inverted clock signal CLK by running the output of a 555 timer in astable mode through a 7404 inverter, and the true CLK output through two 7404 inverters. Since the typical propagation lag through a 7404 inverter is 8 to 12 nanoseconds, the CLK signal lags behind the CLK signal and overlaps it slightly.

The six phases of execution in the SAP-1's instruction cycle are controlled by a six flip-flop ring counter that is clocked by the CLK signal. The Program Counter is a 4-bit ripple counter with the low-order flip-flop clocked by the CLK signal. Since the SAP-1's PC is only supposed to increment during the T1 phase, the J and K inputs of the PC's flip-flops are driven by the T1 phase signal. The intent is for J and K to be high during T1 causing this FF to toggle, and low during the other phases causing it to hold its state. My simulations showed that due to the 74107's sensitivity to its J and K inputs when the CLK input is high, this low-order flip-flop would toggle twice as often as it should: once during T1 and again during T2.

Over the weekend I found a Motorola MC7404P manufactured in 1971 in a dusty box. I suspect this dates back to my Science Fair project of the mid 1970s. This evening I wired it into the clock generation circuit, thus matching the ring counter, program counter, and clock driver portions of original SAP-1 design exactly. Here's what the circuit looks like on my breadboard:

The two chips in the top row are the 74107s forming the four bits of the Program Counter. The first three from the left on the bottom row are the 74107s forming the six bits of the ring counter. The chip on the bottom right is a 556 dual timer (I couldn't find a 555 in my parts bin) and the chip between the 556 and the 74107s is my 7404 hex inverter. The blue push-button switch pulls the CLR line low, as the SAP-1's ring counter is not self-initializing.

Using my oscilloscope I verified all the signals were wired where they should be. I then connected three probes as follows:
  • The yellow trace is the output of the high-order bit of the Program Counter.
  • The blue trace is the output of the low-order bit of the Program Counter.
  • The red trace is the T1 phase signal, which is high during the T1 phase. The T2 phase follows immediately after the T1 period.
Here's the output using the 74107 Master/Slave J/K flip-flops:

Note that the low order bit changes state twice per instruction cycle, once during the T1 phase and again during the T2 phase. This is because the J and K inputs to the low-order FF are high for a short period after its CLK input goes high during T2. This is exactly what the simulation predicted!

For comparison, I replaced the 74107 that represents the two low-order bits of the Program Counter with a 74LS107A edge-clocked chip. No other changes were made to the circuit, and none were made to the 'scope. Here's the output:

This is how the Program Counter is supposed to work. The low-order bit now changes state only during the T1 phase, rather than during T1 and T2. With the low-order bit incrementing only once per instruction cycle, the period of the high-order bit doubles as well.

I think that pretty much proves my point: The SAP-1 will only work if the Program Counter uses edge-clocked flip-flops like the 74LS107A. It will fail if Master/Slave flip-flops like the 74107 are used.

I have other, minor issues with the SAP-1 design. For example, only the lowest bit of the PC needs to be gated with the T1 phase signal. The other flip-flops in the PC would work properly with their J and K inputs tied high. This would reduce the load on the T1 signal by 3 and make the operation more obvious.

If anyone is inclined to build an SAP-1, as of this writing, Jameco Electronics stocks all the parts needed, even though many are obsolete and no longer manufactured.

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