Since I'd tested a structural simulation of the 74107 master/slave J/K flip-flop, I thought it appropriate to also test a structural simulation of the 74LS107A edge-triggered J/K flip-flop. The datasheet for the SN74LS107A from Texas Instruments provides a schematic for their chip, so I started there:
Here's my structural Verilog translation:
The timing for this doesn't match that given in the datasheet, but for the purposes of my tests it doesn't matter as long as there is some propagation delay through each gate.
Both the ring and program (binary ripple) counters work, with some short glitches in the outputs about 18 ns after the falling edge of the clock. However, in the full SAP-1 configuration, it works perfectly with no double counting. The fact that this circuit is not sensitive to changes in J and K while the clock is high makes all the difference.
Thus I repeat my assertion from the previous post: The SAP-1 circuit will not work with a 74107 master/slave flip-flop in the program counter. This also means that Section 8-4 of the textbook is incorrect as written. The use of an edge-clocked device like the 74LS107A is essential in these circuits.
I now feel the urge to get a few 74107 and 74LS107A chips and prove this on my bench. Normally I'd just tack on the extra parts to my next DigiKey order, but they don't stock the 74107 as it's obsolete. Jameco says they stock both the original 74107 and the 74LS107, so I placed an order for some. After I get a chance to run some tests with them I'll post my results.