Apparently I woo-hooed too quickly. I decided to run some simplistic simulations with LTspice to see what would happen with two boards connected to the output of a TC4427A. It wasn't good.
At first I thought this was going to be easy. Microchip provides a Spice model for the TC4427A that LTspice seems happy to process. I'd given no thought to the clock tracks acting as transmission lines when I did the board layout, so I pulled up the board in Eagle and checked the width of the clock tracks (8 mils). The PCB-Pool specifications for a 4-layer board give the distance between outer layer tracks and the interior ground or power plane as 0.38mm. Plugging this into the PCB calculator that comes with KiCad I see these tracks have an impedance of about 88 ohms.
For the initial simulation I created a 1.5ns (~8 inch) transmission line with an 88 ohm impedance. I didn't want to fiddle with transistor simulations yet, so as a starting point I put a 50pF capacitor to ground on the end of the line. This shows the rising edge overshoots by almost a volt with some oscillation that damped out fairly quickly. The falling edge undershoots (goes negative) by almost 2 volts, oscillates for a few cycles (about 25ns) then settles. That's not great.
There are a couple of mitigations already in the design that weren't in my initial simulation. The FDV301N
has a protection diode from ground to its gate. While I found this
limits the use of the FDV301N in some circumstances, adding such a
diode across the load capacitor in my simulation limits the initial
negative excursion on the falling edge
to -0.7V and greatly shortens the oscillation period in the "low" state.
Then I added a second transmission line with its own capacitive load. The Instruction Decoder and Arithmetic Logic Unit boards are currently laid out as 6-layer boards. Using 8 mil traces and the PCB-Pool stack-up these end up as 101 ohm tracks. I can get 88 ohms by using 12 mil tracks, but I decided to make the second transmission line 1ns and 101 ohm. The result is ringing, which I'm assuming is from the reflections from one load traveling back down the other transmission line and back again. This ringing goes on for the entire 200ns duration of the "high" state, and on the "low" state for as least as long. Not good.
The datasheet for the TC4427A gives its output resistance as about 10
ohms. Disconnecting the second transmission line I added an 78 ohm source termination resistor between the TC4427A
the first transmission line. This eliminates the over- and under-shoot, but with the second transmission line reconnected the ringing returns. A smart option would be to add a series termination resistor in front of each transmission line to match the board characteristics (88 or 101 ohms), but I've already built the IP board. It would take a bit of surgery on narrow tracks to splice in such resistors, and that's not something I want to do if I don't absolutely have to.
The next thing I tried was to put a 40 ohm resistor at the output of the TC4427A. I also added a 51 ohm resistor at the input of the second transmission line. This gives me a 38 ohm mismatch to the first line, but a proper 101 ohm match to the second. Hey! This looks pretty good! A few small wiggles on the first line, probably because of the mismatch, and none visible on the second.
Just to be sure of this approach I added a third transmission line. I made this one an 88 ohm track but with a length of 0.7ns. I added a 1 µΩ resistor as a placeholder on the input of its transmission line. The simulation shows ringing, which is kinda what I suspected would happen. However, changing the input resistor to 38 ohms gives nice, clean transitions.
Here's the resulting schematic from LTspice:
And the waveforms it generates:
Of course these simulations are incredibly crude. I have one capacitor and one diode representing a number of dissimilar transistors spread over a fair distance. I'm sure the actual clock lines will be nowhere near as clean even if there is proper termination -- I'll have to pull out the IP board and put a scope probe on the clock lines to see. Regardless, the simulations suggest it's worth some effort to isolate the clock lines on each board from its neighbors by using series resistors on each board.
This technique is pretty much what Doulgas Brooks describes in his article Controlling Impedances When Nets Branch Out, except without the parallel termination resistors. I'm still hoping the slow rise and fall times will allow me to avoid more termination circuitry. I may try to simulate the layout of the IP board and compare that with the actual board.
Until then I'm still facing a choice. I can use this hybrid system of putting series resistors on each of the new boards and just hope that any problems on the IP board don't affect the others, or I can move the two clock signals to other pins for later boards and put series resistors on the driver board for the IP board. Decisions, decisions...