With nominal gate delays added to all the TTL parts in my SAP-1 Verilog simulation, I decided to give the Master/Slave version of the 74107 J-K flip-flop one more try. And it flopped.
At first I tried the behavioral implementation of this device, using a final pair of assign statements to insert the inertial delays given in the datasheet. The code looked like this:
This worked in the single unit test and in the ring counter test. In the program counter test it counted properly but generated a number of glitches as the counter advanced.
Thinking might work better with a structural implementation, I created yet another version using nand and not gates. Here's the schematic view of this implementation:
My unit test produced timing very close to that given by the datasheet. The total delay with low-to-high output transitions is a couple of nanoseconds longer than the datasheet maximum number, but the high-to-low output transitions are a few nanoseconds under the datasheet maximum. I consider that a completely valid simulation.
Again, the ring counter gives acceptable results, but the program counter has noticeable glitches. Trying it in the full SAP-1 simulation produced erroneous calculations, as the sensitivity of the flip-flop to changes in the J and K inputs while the clock is high caused the PC to increment twice per CPU cycle: appropriately in the middle of state T2, and inappropriately in the middle of state T3.
Given that this simulation runs properly with the simulated edge-triggered 74LS107A parts regardless of delays, I'm going to conclude that the SAP-1 would not be reliable and might not work at all using the Master/Slave 74107 parts.