Ideally I'd use an IBIS simulator and the models provided by Xilinx for this purpose. Unfortunately I don't have access to one. The best I can do at the moment is some simulations with LTspice. Still, these are instructive.
Let's start with the circuit model. All of the simulations below were run with the same basic model, with some minor changes in connectivity and values as noted.
V1 represents the output of the Spartan 6's CCLK pin. For the purposes of simplicity I assumed rise and fall times of 1ns. The datasheet gives the pin an input capacitance of 10 picofarads, and I've assumed an output impedance of 34 ohms. As I get more familiar with the IBIS model I'll be able to tweak these, but they're good enough for a first look.
T1 is the transmission line between the FPGA output pin and the Flash chip's clock input, and R1 and C1 represent the input impedance and capacitance of the clock input pin. In Spice the length of a transmission line is specified in time rather than distance; recall that the signal will propagate about 6 inches in 1 nanosecond.
For parallel termination I've set up a Thevenin-equivalent 50 ohm terminator using V2, R2, and R3. This is only connected in the second of the five simulation runs. R4 represents a source (series) termination resistor. Spice doesn't like 0-ohm resistors, so I've set it to 1 micro-ohm when I want it out of the circuit.
Now we're ready to look at the first screen capture. This is set up with a 1ns (6 inch stripline) transmission line and no termination at either end. The red "V(end)" trace shows what the Flash chip would see, and aside from a bit of overshoot on the rising edge and undershoot on the falling edge, it doesn't look too bad. It makes a clean transition through the "no man's land" between the high and low threshold voltages, and none of the bounces get really close to a threshold.
|Unterminated 6" CCLK line|
Xilinx strongly recommends terminating the CCLK line with a Thevenin-equivalent parallel terminator. The second screen capture shows the result of this.
|Thevenin-terminated 6" CCLK line|
Why not use source (series) termination? Here's I've disconnected the parallel termination and changed the source termination resistor to 16 ohms, making the source impedance match that of the transmission line.
|Source-terminated 6" CCLK line|
The previous three simulations have been run assuming a 1ns, or 6-inch stripline, transmission line. As I mentioned in the previous post, if the transmission line is short enough that the round-trip time is less than the rise time of the signal, it starts to look like a lumped circuit rather than individual parts. I'm putting the Flash chip right next to the FPGA, and the total length of the CCLK circuit is just under an inch. What does that look like?
|Source-terminated 1" CCLK line|
Hmm... do I even need the source termination resistor, or can I just connect the CCLK pin straight to the Flash chip?
|Unterminated 1" CCLK line|
One of my concerns is that by making my board layout flexible — having both source and parallel termination footprints — I may be introducing impedance discontinuities that will make the signal worse rather than better. I sure wish I had a proper IBIS PCB simulator!