Tuesday, June 5, 2018

Terminator Two

Let's take another look at the termination of the transmission line for the CCLK signal. (And yes, I do like my puns.)

Ideally I'd use an IBIS simulator and the models provided by Xilinx for this purpose. Unfortunately I don't have access to one. The best I can do at the moment is some simulations with LTspice. Still, these are instructive.

Let's start with the circuit model. All of the simulations below were run with the same basic model, with some minor changes in connectivity and values as noted.

V1 represents the output of the Spartan 6's CCLK pin. For the purposes of simplicity I assumed rise and fall times of 1ns. The datasheet gives the pin an input capacitance of 10 picofarads, and I've assumed an output impedance of 34 ohms. As I get more familiar with the IBIS model I'll be able to tweak these, but they're good enough for a first look.

T1 is the transmission line between the FPGA output pin and the Flash chip's clock input, and R1 and C1 represent the input impedance and capacitance of the clock input pin. In Spice the length of a transmission line is specified in time rather than distance; recall that the signal will propagate about 6 inches in 1 nanosecond.

For parallel termination I've set up a Thevenin-equivalent 50 ohm terminator using V2, R2, and R3. This is only connected in the second of the five simulation runs. R4 represents a source (series) termination resistor. Spice doesn't like 0-ohm resistors, so I've set it to 1 micro-ohm when I want it out of the circuit.

Now we're ready to look at the first screen capture. This is set up with a 1ns (6 inch stripline) transmission line and no termination at either end. The red "V(end)" trace shows what the Flash chip would see, and aside from a bit of overshoot on the rising edge and undershoot on the falling edge, it doesn't look too bad. It makes a clean transition through the "no man's land" between the high and low threshold voltages, and none of the bounces get really close to a threshold.

Unterminated 6" CCLK line
On the source side, though, things are different. The "V(pin)" trace is almost invisible because it's overlaid with the "V(src)" trace, but there is an obvious flat spot half way through each transition. This is entirely predictable. When the output driver turns on, the pin is in the middle of a voltage divider formed by the driver's output impedance to the 3.3V rail and the transmission line's impedance to ground, so it rises to 3.3V * (50 / (34 + 50)) = 1.96V. It's not until the wave travels down to the far end of the transmission line and the reflection travels back that it continues its rise to 3.3V. During that 2ns round-trip time it's just below the 2.0V minimum level to be read as a "high" value. It wouldn't take much variation in the parameters I've used in my simulation to make this dip cross back and forth across this threshold, so this circuit would be prone to errors.

Xilinx strongly recommends terminating the CCLK line with a Thevenin-equivalent parallel terminator. The second screen capture shows the result of this.
Thevenin-terminated 6" CCLK line
Here we see nice, clean transitions on both ends of the transmission line. That's because there is no reflection from the far end, as the terminator makes it look like the transmission line is of infinite length. There is a penalty for this, though: the signal levels are significantly reduced. In fact, others have commented that with the initial configuration of an 8mA drive strength, neither end actually reaches the required input thresholds. Apparently this circuit works, and works reliably enough that Xilinx says this termination method is required. Maybe it looks different using a proper IBIS simulation. But as I've mentioned, this circuit also dissipates 109mW with the pin driven to either 0 or 1.

Why not use source (series) termination? Here's I've disconnected the parallel termination and changed the source termination resistor to 16 ohms, making the source impedance match that of the transmission line.
Source-terminated 6" CCLK line
 Adding a source termination resistor causes the voltage on the pin to differ from the voltage on the source-end of the transmission line. This is essentially a 3-resistor divider, and the pin voltage leads the transmission line. It's enough to push the pin over the "high" threshold and keep it there on the rising edge, while staying a safe distance from the "low" threshold on the falling edge. It also eliminates the over- and under-shoot on both transitions. The real advantage is that it draws no current at all in either quiescent state.

The previous three simulations have been run assuming a 1ns, or 6-inch stripline, transmission line. As I mentioned in the previous post, if the transmission line is short enough that the round-trip time is less than the rise time of the signal, it starts to look like a lumped circuit rather than individual parts. I'm putting the Flash chip right next to the FPGA, and the total length of the CCLK circuit is just under an inch. What does that look like?
Source-terminated 1" CCLK line
Here is the previous source-terminated circuit with the one-way propagation time cut to 167ps, or about a 1 inch stripline. This is about as clean as I could ask for. It's even cleaner that the Thevenin-equivalent terminated 6" line. Again, this is predicted, but it's interesting to see.

Hmm... do I even need the source termination resistor, or can I just connect the CCLK pin straight to the Flash chip?

Unterminated 1" CCLK line
It looks to me like I might be able to do without any termination components at all. Especially when you consider that I'm using a microstrip line rather than a stripline (signals on a microstrip propagate faster than on a stripline, allowing longer tracks for the same propagation time).

One of my concerns is that by making my board layout flexible — having both source and parallel termination footprints — I may be introducing impedance discontinuities that will make the signal worse rather than better. I sure wish I had a proper IBIS PCB simulator!

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