Fixed a latch in the Instruction Decoder

I found a lingering transparent latch in the implementation of the Instruction Decoder module, and I replaced it with a clocked flip-flop. I did a double-check of the Verilog sources, and I think that's the last one. 

The OpenCores repository has been updated.

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Speaking of OpenCores... When I went to update my project, I discovered the site's encryption certificate has expired. And I still haven't gotten a reply to my report of the out-of-date download tarball. I'm not getting a good feeling about the future of the site.

Maybe someone should archive the site?

OpenCores project download failures

It appears the MCS-4 project download link on the OpenCores site points to a tarball created in 2019. I've emailed the OpenCores site maintainers to alert them, but I don't know how long it will take them to correct the problem.

In the meantime, I've created my own tarball of these sources and placed it on Google Drive:

Download link: mcs-4_20220103.tar.gz
File size: 1456944 bytes
MD5 checksum: e2ee2aa03b7dfefd5f10d3e2a6323889

Big Verilog source update on OpenCores.org

November 15th, 2021, marked the 50th anniversary of the release of the MCS-4 chipset. I figure this is as good a time as ever to update my MCS-4 project on OpenCores.

 Here's a summary of the changes:

• Created subdirectories under rtl/verilog for each of the four initial MCS-4 chips. 
• Moved the i4004 CPU-specific Verilog module files into the i4004 subdirectory.
• Updated the i4004 CPU Verilog modules with a few bugfixes.
  
• Published Verilog modules for the i4001 ROM, i4002 RAM, and i4003 Shift Register chips.

These are the Verilog sources I used in my Busicom 141-PF re-creation using a gutted Canon P170-DH calculator, so I'm pretty sure they work correctly.

Let me know if you find these files useful, or if you find what you think is a bug.

 

This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License

My first DMCA Takedown notice

No, no one is asking me to take down this blog or my OpenCores project. Instead, someone "scraped" the OpenCores site and pulled all the various projects into a single repository hosted on GitHub.

It leads to the Source...

I've finally had time to post the Verilog source for the 4004 CPU to my OpenCores project.

The sources posted synthesize for the Xilinx Spartan-3e using the WebPack edition of ISE 12.4 XST, and simulate using ISim. They also synthesize using the Lattice iCEcube2™ tool chain for the HX40 series, though I haven't tried loading that yet.

I haven't yet posted the test bench code, nor have I posted the code implementing the 4001 ROM chip. I'll get around to this sooner or later, I promise.

I have this fantasy of finishing the layout of the remaining boards in time to populate them over the christmas holidays, but realistically that's unlikely to happen. It's somewhat more likely that I'll do some layout during the holidays, get them fabricated in January, and work on them over the following months.

No code posts this weekend

Firstly, work is sucking up my time, and I literally haven't touched the code since early last week. Secondly, my lawyer friend is totally saturated with end-of-quarter work and hasn't been able to review my proposed license disclosure verbiage.

So I won't be posting the Verilog source code for my 4004 CPU implementation this weekend. Rest assured, though, it will come, and will be under the same Creative Commons non-commercial license as the original Intel materials.

OpenCores project created

A couple of days ago I created a project on the OpenCores.org website for the Verilog version of the MCS-4 components. There's a direct link to the project here, or you can look under the "Processor" projects.

The project is currently empty, other than a general description and a couple of links. Since the Verilog is derived directly from the Intel schematics, I want to make sure all of the Verilog source files have appropriate copyright and license notices before posting them. This may happen this weekend.

I've started to notice an up-tick in the number of hits on this blog from that project. For those of you looking for more background on the Verilog aspect of this blog, here are a few links to some of the early entries in this blog you may find most helpful:

• The World's First Microprocessor
• Some Backstory
• Creating a test jig
• Test jig firmware
• Full Circle 
• Dynamic Problems, Static Solutions

That should be enough to get you started. I've also begun tagging the postings based on their content.