Friday, July 6, 2012

Incrementer placement

I had a couple of unexpected free hours last night, so I placed most of the "incrementer" circuit on the Instruction Pointer board. This circuit handles the normal incrementing of the instruction pointer from one instruction to the next, without requiring use of the ALU.

In this screenshot, the incremeter circuit is made up of the four groups below the DRAM array. I haven't routed them yet, so things may get rearranged a bit. The incrementer does its job in three 4-bit nibbles, presumably to save area. The group that handles the carry from one 4-bit nibble to the next hasn't been placed, but will live just to the right of the D0 group on the right.

Also visible are the Effective Address and Refresh counter groups along the far right edge. From top to bottom they are EA bit 0, EA bit 1, Refresh bit 0, and Refresh bit 1. If you click on the image to zoom in you'll see the footprints for the two capacitors I added below the EA bit 1 group in case this bit loses state too rapidly (see the previous posting for an explanation of the design flaw).

The best news is that I have about 73% of the components placed on this board, and what looks like plenty of space for the rest. I'm hoping to get the rest placed this weekend.

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