Thursday, July 26, 2012

Slow progress

It's been a while since my last update. I've been busy with work, and haven't had much of a chance to focus on this project. However, I did get the rest of the circuit blocks routed, and I'm down to 50-some airwires.

The remaining tasks are:
  • Finish routing the connections between the circuit blocks.
  • Define the inter-board connector pin-out.
  • Route the inter-board connector.
  • Add some bypass capacitors between the VDD and GND planes
 After this, the board should be ready for fabrication. I've chosen PCB-Pool for fab, and the routing  complies with their design rule check requirements. One of the reasons for this choice is that they do an electrical test of all 4- and 6-layer boards they produce as part of the basic cost. Most other board houses either charge an extra $150+ for this, or don't offer the service. With about 600 discrete components on this board, most with at least one via to a power plane, the electrical test will save me hours of hair pulling.

I'm tired of posting screenshots that don't look any different that the previous picture. I considered posting that picture of a bunny with a pancake on his head, but it's been overdone. I just stumbled on a pic of the single bit DRAM cell on a breadboard, so I decided to post that:

This was when I was still trying to figure out how important the "bootstrap loads" were to the operation of the system. Rather than using lower-value passive resistors for this, I was considering using PNP transistors in a current mirror configuration; the three TO-92 components in the upper right of the breadboard are two active loads and the current reference. Also note that all the MOSFETs are BSS83s, as this predated my experiments with the FDV301s.

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