Sunday, July 1, 2012


Since I can't, and don't want to, create one single board, the next task was partitioning the design into manageable pieces. Here's the partitioning as depicted in one of Intel's own datasheets:

Each of the two DRAM arrays, the Instruction Pointer and the Scratch Pad, form distinct blocks. This is also clear from looking at the schematic in my previous posting: the Instruction Pointer is the upper left group, the Scratch Pad the upper right group. Other blocks of significant complexity include the Instruction Decoder and the Arithmetic Logic Unit.

As you can imagine, dealing with a single schematic sheet taller than I am would be unwieldy. Also, to be able to lay out separate boards the schematic needed to be broken into one or more sheets per board. After partitioning, the sheets making up each board can be copied to a new schematic and the board laid out from that.

I settled on ANSI "D" size (22" x 32", or about ISO A1) for my schematic sheets. This avoided having to break most of the big blocks into pieces, the Instruction Decoder being the exception. With a 2:1 reduction, this prints nicely on an ANSI "B" sheet (11" x 17", roughly ISO A3), a commonly available size that fits through my color inkjet printer. At this size the text is a bit hard to read, but the structure is easy to follow.

I wrote an Eagle User Language Program (ULP) to print a report of component counts on each sheet. By tagging each sheet with a board assignment label, the ULP also reports the component totals for each board. I wanted to minimize the number of boards, while maintaining the functional groupings. Another ULP that reports the inter-board connections helped guide the partitioning.

Here's the current partitioning, by sheet and by board:

Sheet  1:  Ts: 226  Rs:  18  Bs:   4  Total:  248  Instruction Pointer DRAM Array
Sheet  2:  Ts:  55  Rs:  13  Bs:   0  Total:   68  IP Incrementer
Sheet  3:  Ts:  40  Rs:  16  Bs:   0  Total:   56  IP Row & Refresh Counters
Sheet  4:  Ts:  44  Rs:  15  Bs:   0  Total:   59  IP Column Decode Logic
Sheet  5:  Ts:  53  Rs:  18  Bs:   3  Total:   74  IP Selection Logic
Sheet  6:  Ts: 272  Rs:  20  Bs:   8  Total:  300  ScratchPad DRAM Array
Sheet  7:  Ts:  75  Rs:  19  Bs:   0  Total:   94  ScratchPad Decode & Refresh
Sheet  8:  Ts:  77  Rs:  24  Bs:   5  Total:  106  ScratchPad Selection Logic
Sheet  9:  Ts: 203  Rs:  45  Bs:   2  Total:  250  Instruction Decode 1
Sheet 10:  Ts: 134  Rs:  34  Bs:   1  Total:  169  Instruction Decode 2
Sheet 11:  Ts:  46  Rs:  19  Bs:   2  Total:   67  Instruction Decode 3
Sheet 12:  Ts: 234  Rs:  52  Bs:  15  Total:  301  Arithmetic Logic Unit
Sheet 13:  Ts: 110  Rs:  32  Bs:   5  Total:  147  Chip Select Logic
Sheet 14:  Ts:  81  Rs:  15  Bs:  12  Total:  108  Clock & Timing Generation
Sheet 15:  Ts:  99  Rs:  21  Bs:   9  Total:  129  I/O Buffers - D0..D3

 Instruction Pointer:  Ts: 418  Rs:  80  Bs:   7  Total:  505
         Scratch Pad:  Ts: 424  Rs:  63  Bs:  13  Total:  500
  Instruction Decode:  Ts: 383  Rs:  98  Bs:   5  Total:  486
                 ALU:  Ts: 344  Rs:  84  Bs:  20  Total:  448
        Timing & I/O:  Ts: 180  Rs:  36  Bs:  21  Total:  237

As you can see, I have five boards planned. The first four contain the majority of the circuitry, with the fifth board left as a sort of "catch-all" for what doesn't fit on the others. My rough area analysis suggests this will work, but as a novice creating such complex boards I'm allowing for the possibility that I could be wrong. There's room on the "Timing and I/O" board for some overflow, and the inter-board connectors have plenty of unused pins.

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