Deeper into the mystery

Continuing from the previous post, I zoomed in so each horizontal division represents a mere 5ns rather 500ns, and triggered on the falling edge of row read enable. It's not at all clear to me what is going on, so if you see problems with the following analysis PLEASE let me know!

The first 'scope trace is with the BSS83 as the read enable gate. What we see is Vgs goes from about +2.1V to -4.0V before stabilizing at -3V. The excursion below ground level is likely due to my use of a solderless breadboard. The important point is that turning off this FET doesn't cause a change in Vds or the drain voltage. I attribute that to the tiny internal capacitances in the BSS83 and the grounded substrate.

Now we substitute a DMN26. We see a very similar change in Vgs, but this time we lose a bit of the voltage on the drain. We lose even more voltage on the source, resulting in an increase in Vds. Interestingly, even with these losses the drain ends up a tiny bit higher than it did with the BSS83 due to the DMN26's lower Vgs[th] and correspondingly higher initial level.

Finally we try the FDV301.

As Vg falls, both Vd and Vs fall. Vds is zero for the first 4ns, suggesting the FET is still conducting. I'm guessing that the voltage loss is caused by the gate charge transfer.

As Vgs reaches about -0.6V there is a change in its ΔV/Δt, which could be the gate-source protection diode starting to conduct. There's another at  about Vgs = -1.1V, which coincides with a a stabilization of Vd at 2.0V while Vs continues to fall, resulting in a rise in Vds; this suggests to me the FET has turned off. Vs continues to fall as Vg falls but it doesn't go anywhere as low as with the other two FETs, again perhaps a result of the diode. Even as Vg rebounds from its below-ground excursion Vs continues to fall, eventually settling at about one diode drop above ground.

Unfortunately, Vd fails to remain at 2.0V; this is why the FDV301 is not suitable in this circuit. Seemingly paradoxically Vd rises about 0.3V, then resumes its fall until goes negative, both in respect to ground and to Vs. The disconnect between Vd and Vs reinforces my thought that the FET is off from the point these signals diverge.

What's causing the drain to fall? Why does Vds go negative? I'm really not sure. If anyone out there has a suggestion, feel free to make it!