Now that I understand the function and operation of the "bootstrap load" circuit, I thought I should go back and reevaluate my assumptions and implementation.
Analysis suggests, and experimentation confirms, bootstrap loads have little to do with signal rise-time and everything to do with voltage margins. I had been expecting to see them used when the capacitive load was high, but these are driven by push-pull "totem pole" circuits. Instead they're used to pull up the gates of pass transistors, or to pull up the gates of the high-side push-pull drivers that drive pass transistors. I could probably replace all of them with the same 4.7K resistors I used for the normal loads.
This triggered a bit of anxiety: I know my IP board works, but how close is it to failing? Is it just barely working, or is there margin for component variation? In this, the BSS83 gave me the most cause to worry. Its gate threshold voltage is unhelpfully specified as being "greater than 0.1 and less than 2.0 volts". The thing is, I have no real choice but to use it for the pass transistors; every other choice is either crazy expensive or has gate capacitances of several hundred picofarads.
Since I couldn't get to my lab until late this evening I gave some thought to alternative solutions, if there were a problem. One was to raise Vdd above 5V, which had been chosen somewhat arbitrarily. The limiting factor here is the FDV301, which has an absolute maximum Vgs of 8V, followed by the BSS83's max Vds of 10V. I expect the only negative effect of raising Vdd to 6V or even 7V would be increased power consumption. If that were the only cost of making the design work, it'd be worth it.
Once I got to my lab, though, I was able to measure actual voltage margins under controlled conditions on my breadboard. The randomly-chosen BSS83s I tested in a pass transistor configuration limit the passed voltage in either direction to 1.33V less than the gate voltage. The worst-case scenario is a BSS83 pass transistor, whose gate is being driven by a BSS83 high-side push-pull driver (Vdd - 1.3V), and whose output is driving a BSS83 in a common-source inverter configuration. In this configuration, the noise margin is significantly reduced. Since signals are gated onto and off the data bus through sequential pass transistors I worried that this effect would be cumulative, but it isn't.
With a handle on the situation I finally ran the margin tests on my breadboard, as I said I was going to do three years ago. The worst-case circuit fails with Vdd below 3.5V (the inverter doesn't turn on). Between 3.5V and 4.0V the circuit runs with increased propagation latencies and slow signal transitions compared to 5V operation. Above 4.0V and up to 7.0V (the highest I tested) the circuit is stable, with a very small reduction in latencies up to about 6V. Replacing the high-side driver with an FDV301, as described in the post Unexpected results, or a DMN26 reduces the high-side driver loss to 0.6V, which improves the margins such that it will just barely operate at 3.0V. This gives me confidence that the entire circuit should work at 5.0V, though I will make sure I don't do anything to prevent raising Vdd to 6V if need be.
There's one more step I may take as I work toward completing this project. In the intervening three years I have hand-assembled several dozen boards using 0402 (0.50 x 1.00 mm) passives. After that the DMN26D0UT in its SOT-523 (0.80 x 1.60 mm, about 0603) packaging no longer scares me. I'm seriously considering using it to replace the BSS83 as the high-side driver in the tristate output circuits, where the FDV301 can't be used because of its gate-to-source protection diode. Its lower Vgs[th] would increase the output-high voltage by almost a half a volt.