Co się dzieje w Polsce?

What is happening in Poland?

This is not the most popular blog in the world, but I do get views from just about every country in the world. Over the last few months, though, my views from Poland have risen until they account for more than half of views for any given period. Did I become required reading for an Electrical Engineering class? Or maybe a Technical English class?

Edited 2013-08-17 to add:

Apparently these accesses are what is known as "referer spam" (sic). Some people put a widget in their blogs that automatically provides links back to those sites which bring them the most traffic. By bombarding a blog with fake views, the back-links to these fake referrals cause the spamming site to rise in search engine rankings. Most of these fake referrals link to porn or malware sites.

Since I don't provide such automatic back-links, and I never click on any suspect referral link, their spamming does nothing but screw up my statistics. Fortunately, my stats are merely a curiosity for me.

ALU board component placement done

Just a quick snapshot of the Arithmetic/Logic Unit board before I call it a night. I got all the remaining components roughly placed. When I place components I'm always considering how to route signals, but I expect to have to do a little rearranging when I actually route them.

And there are a lot of signals to route. A ratsnest command reports 1100 airwires, including 326 GND and 135 VDD. Like the Instruction Decode board, this board has a full ground plane on layer 2, but VDD will have to be routed like any other signal.

ALU board layout update

Since I've moved the Instruction Decode board along a good way, I decided the Arithmetic/Logic Unit board needed some attention.

Part of the problem with putting a project on hold like I sometimes do is that all the details of where you left off get flushed from mental cache, and it can take a half an hour or more just to figure out what needs doing. With the ALU board it appears I'd left off with only 21 FETs and 10 resistors unplaced, but almost nothing had been routed. With that figured out I settled in to place the rest.

I thought someone out there might want to see what my screen looks like doing this. I have a 30-inch, high-resolution (2650x1600 pixels) monitor, which allows me to display both the active portions of the schematic and the board layout at the same time without having to squint.

Eagle Schematic and Board Layout views -- i4004 ALU board

In this screen capture, I've just selected transistor T0172, which highlights the part on both the schematic and board windows. The grid displayed on the board is 16 mil squares, which I've found to be about as tightly packed as I'd want to attempt with these parts and my skill level.

We have contact!

Tim McNerney and I have established contact! If that name doesn't ring a bell, it should: he's the guy who envisioned the recreation of the Intel 4004 in the first place, got Intel to make available the schematics, and inspired others to help bring his vision to life. He's also the author of the Intel 4004 — 35th Anniversary Project web page -- if you're interested in the 4004 and haven't read his page, go there NOW.

During our conversations another option for MOSFET choices came to my attention. Rather than searching for one of the scarce few 4-terminal discrete FETs, it's possible to use two devices back-to-back to work around the problems created by the body diode created when the FET's substrate is connected to its source:

In this configuration, the two drain terminals can be used interchangeably, while the gate connection is common. In operation, if the left side drain is positive with respect to the right side the body diode on the right will be forward-biased and will conduct, but the one on the left is reverse-biased and the circuit works as intended when the gate is low. Since the FETs themselves will conduct in either direction, there shouldn't even be a voltage drop across the conducting body diode when the gate is high.

There is a drawback to this approach: the gate capacitance is doubled, since the two gates are in parallel. This will result in higher power consumption and possibly slower operation, especially since the 4004 uses resistive pull-ups rather than push-pull circuits in most cases, though there are push-pull drivers in cases where there is high capacitive loading (like in the DRAM arrays) or where timing is critical (like in the ALU).

Another drawback would appear to be increased parts counts. However, dual-FET parts are pretty common in the SMD world. Consider these two examples:

BSS84W -- Single P-Channel MOSFET

BSS84DW -- Dual P-Channel MOSFET

The package dimensions of these two devices are identical, differing only in the number and placement of the leads.

I think I'm going to add a few of these to my next parts order (along with prototyping adapters) so I can experiment with them. I want to see how they behave in a DRAM cell. That's the best part of hobbies -- there's always something to learn!

Another MOSFET option

Given the spool of several hundred BSS83 MOSFETs sitting on my workbench, I'm pretty well committed to my choice of transmission gate FETs. Out of curiosity, though, in an idle moment I found myself searching yet again for an enhancement-mode MOSFET with a separate substrate connection.

And I found not one, but a whole series of them. A company in Fremont, Californa, called Calogic LLC makes a line of high-speed DMOS analog switches (really MOSFETs) that seem quite suitable for use in a project like this one. It appears to be a drop-in replacement for the BSS83.

Neither DigiKey nor Mouser carry their products. They do have a distributor link on their website, and some of them do sell suitable devices in "small" (less than 2500 unit) quantities. The prices I saw are about 6x that of Mouser's price for the BSS83, but at least there is more than just one device available.

I'm not dead yet!

Life has slowed down enough for me to have a bit of time to spend with my insanity.

As I've mentioned before, my test jig can't drive enough pins to test either the Instruction Decoder or the Arithmetic Logic Unit separately, so these will have to be assembled and tested at the same time. I'd started a basic layout of the Instruction Decoder but hadn't gotten too far. This evening I made some progress.

All the components have been placed, though I'm not happy with the layout in some areas. A lot of the routing has been done, and what's mainly left is interconnecting the large functional blocks and to the off-board connectors.

For those who like numbers, I have 622 airwires remaining, 322 of which are missing vias from component pads to the ground plane on layer 2. Another 109 are to VDD, though since I don't have a dedicated power plane these will have to be routed just like the remaining 191 signals. I also need to add some bypass capacitors, as the original i4004 schematic has none; this will be especially important given the absence of a power plane.

It's a small world

Earlier this week I was at my current client's site and joined a break-room conversation about oscilloscopes. I mentioned having moved up from a 100 MHz Tektronix analog scope to a 1 GHz LeCroy digital scope, and was asked what kind of electronics I do at home. When I mentioned this project, one guy's face lit up: he's a 4004 experimenter! He has two of the real 4004 CPU chips at home, and was quite interested in my efforts to build a discrete component version.

As is apparent from the paucity of posts to this blog since last September, I really haven't been able to spend a lot of time on this project recently. I've taken on new responsibilities with my current client that have kept me quite busy. I do intend to push this project forward when time permits, though.