Monday, March 14, 2016

A sixth board?

When I started this project I was very worried about how I'd test this thing. I didn't want to build all five boards, only to discover I'd made some major mistake that would require scrapping them and starting over. Doing so would not only take a lot of time, but between the cost of the board and the components on it, each assembled board costs around $250. Redoing one would be frustrating and annoying, but if I had to redo all five I might well drop the project.

Rather than build all five boards I've emulated the missing boards by using a Xilinx Spartan 3E FPGA on a board manufactured by Digilent. One of the problems with this is that the expansion interface for the Digilent board only provides 40 I/Os, which is insufficient to test either the Instruction Decoder or Arithmetic Logic Unit boards individually. It's also gross overkill for the job -- I'm using 3% of the on-chip resources and only the power and clock resources on the board.

One of the alternatives I investigated in September 2012 was an FPGA chip from Lattice Semiconductor called the ICE40-HX. This is a modest, very low power FPGA family intended for use in cell phones and other small devices. The reference boards are available for less than $25 (versus $300 for the Xilinx board) and they're easy to interface. It looks like the i4004 design would occupy about 40% of the HX1K part on the reference board, though the VQFP-100 package has only 74 I/O pins which is not as many as I need. The HX4K part is available in a TQFP-144 with 107-ish I/Os and four times the resources for new and creative purposes. I'd love to drop an HX8K part on it, but I'm not yet ready to deal with BGAs even if they're 0.80mm spacing.

Originally I expected the I/O and Timing board to be mostly empty space, and I considered putting this FPGA on it. After moving the Chip Select logic from the ALU board (where it didn't belong) fitting it onto the I/O and Timing board would be tight. It would also disturb the discrete component nature of this project by slapping a set of LSI chips in QFPs on it. It would also prevent the use of the FPGA to generate the signals that the discrete logic on the board generates. So I think I'm looking at a sixth board.

Here's what I'm thinking of putting on this board:
  • An ICE40-HX4K FPGA (TQFP-144) connected to all i4004 inter-board and external I/O signals.
  • A 93LCxx SPI Flash ROM (SOIC-8) to load the FPGA on power-up.
  • An FT2232H USB-2 serial interface chip (LQFP-64) for programming the FPGA bit-file and serial communications with the FPGA.
  • An LT3030 voltage regulator to provide 3.3V and 1.2V power to the FPGA from the +5V (or higher) i4004 supply.
  • A crystal oscillator to provide clocking to the FPGA logic.
  • An LM5111 dual MOSFET driver chip (SOIC-8) to drive CLK1 and CLK2 from the FPGA.
  • Level-shifting FETs (probably FDV301s) for all I/Os.
  • A 20-pin (2x10) ribbon cable connector for interface with my logic analyzer pod.
Why choose the FT2232H and LT3030 chips? Cuz those are the ones on the Lattice reference boards! Proven designs save repeating other people's mistakes. Also I know the FT2232H will work with the Lattice development software, which will save me having to write my own flash programming software.

What might I do with the FGPA?
  • Emulate portions of the i4004 to allow testing of individual boards rather than requiring board sets.
  • Control the data sampling clock and triggering of the logic analyzer to capture complex events, such as the execution of a specific instruction.
  • Emulate the i4001 ROM, i4002 RAM, and i4003 Shift Register chips in a complete system such as the Busicom calculator.
  • Emulate the Busicom calculator keyboard and printer interface through the USB serial interface.

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