Thursday, March 17, 2016

I/O & Timing board progress

I've made good progress on the I/O and Timing board, so I thought I'd share a screen capture of the layout. There are currently 249 unrouted signal airwires, plus another 201 to GND and 92 to VDD.

Across the top is the 8-bit shift register that identifies which of the eight execution phases is current, along with the SYNC signal that identifies the start of an instruction cycle.

The four identical groupings on the lower right side of the board are the bidirectional tri-state I/O buffers for the 4-bit data bus, with D0 at the bottom and D3 at about the middle of the board. Above that is the logic that drives the buffers to be input or output.

The groupings on the left side of the board are the chip select drivers and their associated decode logic. These are the circuits I'd originally assigned to the ALU board before I figured out what they really do.

Speaking of reassigning circuits, note the lone inverter on the lower left corner of the board. This is part of the TEST input, and really belongs on the Instruction Decoder board. This would also eliminate one inter-board circuit, as the TEST_PAD input needs to be routed inter-board anyway for debugging access. One inverter would be trivial to move.

However, the Rev G original schematic has a revision note that reads "Added circuit to TEST input" dated 8-6-76. This replaces the single inverter with the circuit shown here. It appears to be a gated latch, and the feedback makes it look to me like a Schmitt trigger circuit. Maybe I'll test this one in my lab!

It appears the chip that was used to develop the i4004 Analyzer was an older revision, as it has only a single inverter on the TEST input. The two designs are the same from the circuit leading off the right edge onwards. Should I update my board with this new circuit? It looks like there is room either on the IO&T board or the ID board for this circuit.

You'll note I added a 36-pin ribbon cable connector along the bottom edge of the board. This will serve in place of the 16-pin DIP interface of the original i4004 chip. The FETs just above the connector are for input protection -- they have their gates and sources grounded and the drains connect to the I/O pins. One option I'm considering is replacing these with 7.5V Zener diodes, which may be more effective at protecting the circuits from mishandling. I can even get the diodes in a pin-compatible SOT-23-3 package.

Why a connector with so many pins? I wanted a really low-impedance ground to avoid ground-bounce on the cable, and this allows me to put a ground wire between each signal wire for isolation. The CLK1 and CLK2 signals are probably the worst-cases: they switch rapidly (~16ns rise/fall time) at a fairly high clock rate (741 KHz) while driving significant capacitive loads (in excess of 500pF). I really don't want noise bleeding over into adjacent signals.

Similarly, although a single pin and conductor is rated for 1A continuous with a 30C rise, I wanted more than one pin for VDD. The spec for the i4004 chip says it draws 30-40 mA, while I expect my board to draw 250-500 mA depending on how many loads are being pulled to ground on average. This arrangement allows me to devote three pins to VDD without sacrificing isolation.

Finally, using a 36 pin cable allows me to use easily-available Floppy Disk drive cables. Without the twist, naturally.

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