Thinking how to best pin out the rest of the inter-board connections, last night I decided I should also look at the Scratchpad board. To my surprise I discovered I really hadn't gotten much done on this when I shelved this project back in 2013. Looking back at the blog entry I wrote about Scratchpad Array Placement in August 2012 I see I'd done the placement of the rectangular DRAM array components but not much more. Almost none of the signals are routed.
Thus I decided to place the scratchpad refresh counters and the row decode logic. When I placed the DRAM array the layout patterns were fresh in my mind, but that's long since gone. With a second instance of Eagle displaying the Instruction Pointer board I can look at the layout of its counters while working on the SP board. The IP board has a pair of 2-bit counters (Effective Address and Refresh) while the SP board has a single 3-bit refresh counter. Each counter occupies only a 4x4 matrix of 160x160 mil layout grid squares so they're pretty compact. The inter-counter connections are a little different than on the IP board, but not so much to make it worth making big changes to the layout.
I'm left with 27 resistors and 73 transistors unplaced. That's about 36% of the resistors and 17% of the transistors. With more than 160 unoccupied grid squares in a contiguous area I don't expect too much trouble squeezing everything in.