Friday, August 17, 2012

Latest snapshot

It's been a while since I posted a snapshot. Here's the current layout:

There are 24 airwires remaining, most in the lower right corner where the timing and state "bus" connects to inter-board connector. I've deliberately left things there disconnected because that makes it easier to shift the "bus" without getting diagonals off the proper 45 degree angles. And I do plan to shift the "bus" up somewhat, as the bottom traces are below the edge of the VDD/GND planes on the inner layers.

I'm glad this system operates so slowly. After reading relevant chapters in the book I mentioned in the last post I see serious possibilities for ringing. Fortunately, the partitioning I selected keeps most of the fast signals with push-pull drivers contained within a single board. The major exceptions are the main clocks and the eight phase signals, which are distributed to all boards and run all over the place. The clock and timing board is the last board I plan to build, and I'm willing to add some components to control the slew rates of these signals if need be. It's something I'll definitely look for when I get this board built, because the problem will only get worse.

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